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1 fn3179.7 icl7660s, icl7660a super voltage converters the icl7660s and icl7660a super voltage converters are monolithic cmos voltage conversion ics that guarantee significant performance adva ntages over other similar devices. they are direct replacements for the industry standard icl7660 offering an extended operating supply voltage range up to 12v, with lower supply current. a frequency boost pin has been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. all improvements are highlighted in the ?electrical specifications? section on page 3. critical parameters are guaranteed over the entire commercial and industrial temperature ranges. the icl7660s and icl7660a perform supply voltage conversions from positive to neg ative for an input range of 1.5v to 12v, resulting in complementary output voltages of -1.5v to -12v. only two non-critical external capacitors are needed, for the charge pump and charge reservoir functions. the icl7660s and icl7660a can be connected to function as a voltage doubler and will generate up to 22.8v with a 12v input. they can also be used as a voltage multipliers or voltage dividers. each chip contains a series dc power supply regulator, rc oscillator, voltage level translator, and four output power mos switches. the oscillator, wh en unloaded, oscillates at a nominal frequency of 10khz for an input supply voltage of 5.0v. this frequency can be lowered by the addition of an external capacitor to the ?osc? terminal, or the oscillator may be over-driven by an external clock. the ?lv? terminal may be tied to gnd to bypass the internal series regulator and improve low voltage (lv) operation. at medium to high voltages (3.5v to 12v), the lv pin is left floating to prevent device latchup. in some applications, an exte rnal schottky diode from v out to cap- is needed to guarantee latchup free operation (see do?s and dont?s section on page 8). features ? guaranteed lower max supply current for all temperature ranges ? wide operating voltage range: 1.5v to 12v ? 100% tested at 3v ? boost pin (pin 1) for higher switching frequency ? guaranteed minimum power efficiency of 96% ? improved minimum open circuit voltage conversion efficiency of 99% ? improved scr latchup protection ? simple conversion of +5v logic supply to 5v supplies ? simple voltage multiplication v out = (-)nv in ? easy to use; requires only two external non-critical passive components ? improved direct replacement for industry standard icl7660 and other second source devices ? pb-free available (rohs compliant) applications ? simple conversion of +5v to 5v supplies ? voltage multiplication v out = nv in ? negative supplies for data acquisition systems and instrumentation ? rs232 power supplies ? supply splitter, v out = v s pin configurations icl7660s (8 ld pdip, soic) top view icl7660a (8 ld pdip, soic) top view boost cap+ gnd cap- 1 2 3 4 8 7 6 5 v+ osc lv v out nc cap+ gnd cap- 1 2 3 4 8 7 6 5 v+ osc lv v out data sheet january 23, 2013 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 1999, 2004, 2005, 2008, 2011, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn3179.7 january 23, 2013 ordering information part number (note 3) part marking temp. range (c) package pkg. dwg. # icl7660scba (note 1) 7660 scba 0 to +70 8 ld soic m8.15 icl7660scbaz (notes 1, 2) 7660 scbaz 0 to +70 8 ld soic (pb-free) m8.15 icl7660scpa 7660s cpa 0 to +70 8 ld pdip e8.3 icl7660scpaz (note 2) 7660s cpaz 0 to +70 8 ld pdip (pb-free; note 4) e8.3 icl7660siba (note 1) 7660 siba -40 to +85 8 ld soic m8.15 icl7660sibaz (notes 1, 2) 7660 sibaz -40 to +85 8 ld soic (pb-free) m8.15 icl7660sipa 7660 sipa -40 to +85 8 ld pdip e8.3 icl7660sipaz (note 2) 7660s ipaz -40 to +85 8 ld pdip (pb-free; note 4) e8.3 ICL7660ACBA (note 1) 7660acba 0 to 70 8 ld soic (n) m8.15 ICL7660ACBAza (notes 1, 2) 7660acbaz 0 to 70 8 ld soic (n) (pb-free) m8.15 icl7660acpa 7660acpa 0 to 70 8 ld pdip e8.3 icl7660acpaz (note 2) 7660acpaz 0 to 70 8 ld pdip (pb-free; note 4) e8.3 icl7660aiba (note 1) 7660aiba -40 to 85 8 ld soic (n) m8.15 icl7660aibaza (notes 1, 2) 7660aibaz -40 to 85 8 ld soic (n) (pb-free) m8.15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for icl7660s , icl7660a . for more information on msl, please see tech brief tb363 . 4. pb-free pdips can be used for through-hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. icl7660s, icl7660a
3 fn3179.7 january 23, 2013 absolute maximum rati ngs thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0v lv and osc input voltage (note 5) v+ < 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v+ + 0.3v v+ > 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ -5.5v to v+ +0.3v current into lv (note 5) v+ > 3.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20a output short duration v supply 5.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous operating conditions temperature range icl7660si, icl7660ai . . . . . . . . . . . . . . . . . . . . . -40c to +85c icl7660sc, icl7660ac . . . . . . . . . . . . . . . . . . . . . 0c to +70c thermal resistance (typical, notes 6, 7) ja (c/w) jc (c/w) 8 ld pdip* . . . . . . . . . . . . . . . . . . . . . . 110 59 8 ld plastic soic. . . . . . . . . . . . . . . . . 160 48 storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through-hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. connecting any terminal to voltages greater than v+ or less than gnd may cause destructive latchup. it is recommended that no inputs from sources operating from external supplies be applied prior to ?power up? of icl7660s and icl7660a. 6. ja is measured with the component mounted on a low effective t hermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is taken at the package top center. 8. pb-free pdips can be used for through-hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. electrical specifications icl7660s and icl7660a, v+ = 5v, t a = +25c, osc = free running (see figure 12, ?icl7660s test circuit? on page 7 and figure 13 ?icl7660a test circuit? on page 7), unless otherwise specified. parameter symbol test conditions min (note 9) typ max (note 9) units supply current (note 11) i+ r l = , +25c - 80 160 a 0c < t a < +70c - - 180 a -40c < t a < +85c - - 180 a -55c < t a < +125c - - 200 a supply voltage range - high (note 12) v+ h r l = 10k, lv open, t min < t a < t max 3.0 - 12 v supply voltage range - low v+ l r l = 10k, lv to gnd, t min < t a < t max 1.5 - 3.5 v output source resistance r out i out = 20ma - 60 100 i out = 20ma, 0c < t a < +70c - - 120 i out = 20ma, -25c < t a < +85c - - 120 i out = 20ma, -55c < t a < +125c - - 150 i out = 3ma, v+ = 2v, lv = gnd, 0c < t a < +70c - - 250 i out = 3ma, v+ = 2v, lv = gnd, -40c < t a < +85c - - 300 i out = 3ma, v+ = 2v, lv = gnd, -55c < t a < +125c - - 400 oscillator frequency (note 10) f osc c osc = 0, pin 1 open or gnd 5 10 - khz c osc = 0, pin 1 = v+ - 35 - khz power efficiency p eff r l = 5k 96 98 - % t min < t a < t max r l = 5k 95 97 - - voltage conversion efficiency v out eff r l = 99 99.9 - % icl7660s, icl7660a
4 fn3179.7 january 23, 2013 oscillator impedance z osc v+ = 2v - 1 - m v+ = 5v - 100 - k icl7660a, v+ = 3v, t a = 25c, osc = free running, test circuit figure 13, unless otherwise specified supply current (note 13) i+ v+ = 3v, r l = , +25c - 26 100 a 0c < t a < +70c - - 125 a -40c < t a < +85c - - 125 a output source resistance r out v+ = 3v, i out = 10ma - 97 150 0c < t a < +70c - - 200 -40c < t a < +85c - - 200 oscillator frequency (note 13) f osc v+ = 3v (same as 5v conditions) 5.0 8 - khz 0c < t a < +70c 3.0 - - khz -40c < t a < +85c 3.0 - - khz notes: 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 10. in the test circuit, there is no external capacitor applied to pin 7. however, when the device is plugged into a test socket , there is usually a very small but finite stray capacitance present, on the order of 5pf. 11. the intersil icl7660s and icl7660a can operate without an extern al diode over the full temperature and voltage range. this d evice will function in existing designs that incorporate an external di ode with no degradation in overall circuit performance. 12. all significant improvements over th e industry standard icl7660 are highlighted. 13. derate linearly above 50c by 5.5mw/c. electrical specifications icl7660s and icl7660a, v+ = 5v, t a = +25c, osc = free running (see figure 12, ?icl7660s test circuit? on page 7 and figure 13 ?icl7660a test circuit? on page 7), unless otherwise specified. (continued) parameter symbol test conditions min (note 9) typ max (note 9) units icl7660s, icl7660a
5 fn3179.7 january 23, 2013 functional block diagram voltage level translator substrate network osc lv v+ cap+ cap- 7 oscillator and divide-by- 2 counter 6 internal supply regulator 3 logic q 3 3 q 1 v out 3 8 2 q 2 3 4 5 q 4 gnd typical performance curves see figure 12, ?icl7660s test circuit? on page 7) and figure 13 ?icl7660a test circuit? on page 7 figure 1. operating voltage as a function of temperature figure 2. output source resistance as a function of supply voltage figure 3. output source resistance as a function of temperature figure 4. power conversion efficiency as a function of oscillator frequency -55 -25 0 25 50 100 125 12 10 8 6 4 2 0 supply voltage (v) temperature (c) supply voltage range (no diode required) 250 200 150 100 50 0 02 4681012 supply voltage (v) output source resistance ( ? ) t a = +125c t a = +25c t a = -55c 350 300 250 200 150 100 50 0 output source resistance ( ? ) -50 -25 0 25 50 75 100 125 temperature (c) i out = 20ma, v+ = 12v i out = 20ma, v+ = 5v i out = 20ma, v+ = 5v i out = 3ma, v+ = 2v 98 96 94 92 90 88 86 84 82 80 power conversion efficiency (%) 100 1k 10k 50k osc frequency f osc (hz) v+ = 5v t a = +25c i out = 1ma icl7660s, icl7660a
6 fn3179.7 january 23, 2013 figure 5. frequency of oscillation as a function of external oscillator capacitance figure 6. unloaded oscillator frequency as a function of temperature figure 7. output voltage as a function of output current figure 8. supply current and power conversion efficiency as a function of load current figure 9. output voltage as a function of output current figure 10. supply curren t and power conversion efficiency as a function of load current typical performance curves see figure 12, ?icl7660s test circuit? on page 7) and figure 13 ?icl7660a test circuit? on page 7 (continued) 1 10 100 1k oscillator frequency f osc (khz) 10 9 8 7 6 5 4 3 2 1 0 c osc (pf) v+ = 5v t a = +25c oscillator frequency f osc (khz) 20 18 16 14 12 10 8 -55 -25 0 25 50 75 100 125 temperature (c) v+ = 10v v+ = 5v output voltage (v) 1 0 -1 -2 -3 -4 -5 010203040 load current (ma) v+ = 5v t a = +25c power conversion efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 100 90 80 70 60 50 40 30 20 10 0 load current (ma) 0102030 40 5060 v+ = 5v t a = +25c supply current (ma) output voltage (v) 2 1 0 -1 -2 012 345 6789 load current (ma) t a = +25c v+ = 2v 100 90 80 70 60 50 40 30 20 10 0 16 14 12 10 8 6 4 2 0 0 1.5 3.0 4.5 6.0 7.5 9.0 load current (ma) v+ = 2v t a = +25c power conversion efficiency (%) supply current (ma) (note 12) icl7660s, icl7660a
7 fn3179.7 january 23, 2013 figure 11. output source resistance as a function of oscillator frequency note: 14. these curves include, in the supply curren t, that current fed directly into the load r l from the v+ (see figure 12). thus, approximately half the supply current goes directly to the positive side of the lo ad, and the other half, through the icl7660s and icl7660a, goes to t he negative side of the load. ideally, v out 2v in , i s 2i l , so v in x i s v out x i l . typical performance curves see figure 12, ?icl7660s test circuit? on page 7) and figure 13 ?icl7660a test circuit? on page 7 (continued) output resistance ( ? ) 400 300 200 100 0 100 1k 10k 100k oscillator frequency (hz) v+ = 5v t a = +25c i = 10ma c 1 = c 2 = 10mf c 1 = c 2 = 1mf c 1 = c 2 = 100mf 1 2 3 4 8 7 6 5 + - c 1 10f i s v+ (+5v) i l r l - v out c 2 10f icl7660s v+ + - note: for large values of c osc (>1000pf), the values of c 1 and c 2 should be increased to 100f. figure 12. icl7660s test circuit note: for large values of c osc (>1000pf) the values of c 1 and c 2 should be increased to 100 f. figure 13. icl7660a test circuit 1 2 3 4 8 7 6 5 + - c 1 10 f i s v+ (+5v) i l r l -v out c 2 10 f icl7660a c osc + - (note) icl7660s, icl7660a
8 fn3179.7 january 23, 2013 detailed description the icl7660s and icl7660a contain all the necessary circuitry to complete a negative voltage converter, with the exception of two external capacitors, which may be inexpensive 10f polarized electr olytic types. the mode of operation of the device may best be understood by considering figure 14, whic h shows an idealized negative voltage converter. capacitor c 1 is charged to a voltage, v+, for the half cycle, when switches s 1 and s 3 are closed. (note: switches s 2 and s 4 are open during this half cycle). during the second half cycle of operation, switches s 2 and s 4 are closed, with s 1 and s 3 open, thereby shifting capacitor c 1 to c 2 such that the voltage on c 2 is exactly v+, assuming ideal switches and no load on c 2 . the icl7660s and icl7660a approach this ideal situation more closely than existing non-mechanical circuits. in the icl7660s and icl7660a, the four switches of figure 14 are mos power switches; s 1 is a p-channel device; and s 2 , s 3 and s 4 are n-channel devices. the main difficulty with this approach is that in integrat ing the switches, the substrates of s 3 and s 4 must always remain reverse biased with respect to their sources, but not so much as to degrade their ?on? resistances. in addition, at circuit start- up, and under output short circuit conditions (v out = v+), the output voltage must be s ensed and the substrate bias adjusted accordingly. failure to accomplish this would result in high power losses and probable device latch-up. this problem is eliminated in the icl7660s and icl7660a by a logic network that senses the output voltage (v out ) together with the level tr anslators, and switches the substrates of s 3 and s 4 to the correct level to maintain necessary reverse bias. the voltage regulator portion of the icl7660s and icl7660a is an integral part of the anti-latchup circuitry; however, its inherent voltage drop can degrade operation at low voltages. therefore, to improve low voltage operation, the ?lv? pin should be connected to gnd, thus disabling the regulator. for supply voltages greater than 3.5v, the lv terminal must be left open to ensure latchup-proof operation and to prevent device damage. theoretical power efficiency considerations in theory, a voltage converter can approach 100% efficiency if certain conditions are met: 1. the drive circuitry consumes minimal power. 2. the output switches have extremely low on resistance and virtually no offset. 3. the impedance of the pump and reservoir capacitors are negligible at the pump frequency. the icl7660s and icl7660a approach these conditions for negative voltage conversion if large values of c 1 and c 2 are used. energy is lost only in the transfer of charge between capacitors if a change in voltage occurs . the energy lost is defined as shown in equation 1: where v 1 and v 2 are the voltages on c 1 during the pump and transfer cycles. if the impedances of c 1 and c 2 are relatively high at the pump frequency (see figure 14) compared to the value of r l , there will be a substantial difference in the voltages, v 1 and v 2 . therefore it is not only desirable to make c 2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for c 1 in order to achieve maximum efficiency of operation. do?s and don?ts 1. do not exceed maximum supply voltages. 2. do not connect lv terminal to gnd for supply voltage greater than 3.5v. 3. do not short circuit the output to v + supply for supply voltages above 5.5v for extended periods; however, transient conditions including start-up are okay. 4. when using polarized capacitors, the + terminal of c 1 must be connected to pin 2 of the icl7660s and icl7660a, and the + terminal of c 2 must be connected to gnd. 5. if the voltage supply driving the icl7660s and icl7660a has a large source impedance (25 to 30 ), then a 2.2f capacitor from pin 8 to ground may be required to limit the rate of rise of input voltage to less than 2v/s. 6. if the input voltage is higher than 5v and it has a rise rate more than 2v/s, an external schottky diode from v out to cap- is needed to prevent latchup (triggered by forward biasing q4?s body diode) by keeping the output (pin 5) from going more positive than cap- (pin 4). 7. user should ensure that the output (pin 5) does not go more positive than gnd (pin 3). device latch-up will occur under these conditions. to provide additional protection, a 1n914 or similar diode placed in parallel with c 2 will prevent the device from latching up under these conditions, when the load on v out creates a path to pull up v out before the ic is active (anode pin 5, cathode pin 3). v out = -v in c 2 v in c 1 s 3 s 4 s 1 s 2 8 2 4 33 5 7 figure 14. idealized negative voltage converter e 1 2 -- - c 1 v 1 2 v 2 2 ? () = (eq. 1) icl7660s, icl7660a
9 fn3179.7 january 23, 2013 typical applications simple negative voltage converter the majority of applications will undoubtedly utilize the icl7660s and icl7660a for generation of negative supply voltages. figure 15 shows typical connections to provide a negative supply where a positive su pply of +1.5v to +12v is available. keep in mind that pin 6 (lv) is tied to the supply negative (gnd) for supply voltage below 3.5v. the output characteristics of t he circuit in figure 15 can be approximated by an ideal voltage source in series with a resistance as shown in figure 15b. the voltage source has a value of -(v+). the output impedance (r o ) is a function of the on resistance of the internal mos switches (shown in figure 14), the switching frequency, the value of c 1 and c 2 , and the esr (equivalent series resistance) of c 1 and c 2 . a good first order approximation for r o is shown in equation 2: combining the four r swx terms as r sw , we see in equation 3 that: r sw , the total switch resistance, is a function of supply voltage and temperature (see the output source resistance graphs, figures 2, 3, and 11), typically 23 at +25c and 5v. careful selection of c 1 and c 2 will reduce the remaining terms, minimizing the output impedance. high value capacitors will reduce the 1/(f pump x c 1 ) component, and low esr capacitors will lower th e esr term. increasing the oscillator frequency will reduce the 1/(f pump x c 1 ) term, but may have the side effect of a net increase in output impedance when c 1 > 10f and is not long enough to fully charge the capacitors every cycl e. equation 4 shows a typical application where f osc = 10khz and c = c 1 = c 2 = 10f: since the esrs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/f pump x c 1 term, rendering an increase in switching frequency or filter capacitance ineffective. typical electrolyt ic capacitors may have esrs as high as 10 . output ripple esr also affects the ripple voltage seen at the output. the peak-to-peak output ripple voltage is given by equation 5: a low esr capacitor will result in a higher performance output. paralleling devices any number of icl7660s and icl7660a voltage converters may be paralleled to reduce output resistance. the reservoir capacitor, c 2 , serves all devices, while each device requires its own pump capacitor, c 1 . the resultant output resistance is approximated in equation 6: cascading devices the icl7660s and icl7660a may be cascaded as shown to produce larger negative multiplic ation of the initial supply voltage. however, due to the finite efficiency of each device, the practical limit is 10 device s for light loads. the output voltage is defined as shown in equation 7: where n is an integer repres enting the number of devices cascaded. the resulting output resistance would be approximately the weighted sum of the individual icl7660s and icl7660a r out values. changing the icl7660s and icl7660a oscillator frequency it may be desirable in some applications, due to noise or other considerations, to alter the os cillator frequency. this can be achieved simply by one of several methods. by connecting the boost pin (pin 1) to v+, the oscillator charge and discharge current is increased and, hence, the oscillator frequency is increas ed by approximately 3.5 times. the result is a decrease in th e output impedance and ripple. 1 2 3 4 8 7 6 5 + - 10f 10f icl7660s v out = -v+ v+ + - r o v out v+ + - 15a. 15b. figure 15. simple negative converter and its output equivalent icl7660a r 0 2r sw1 r sw3 esr c1 ++ () 2r sw2 r sw4 esr c1 ++ () + () ? (eq. 2) 1 f pump c 1 ------------------------------- - esr c2 + f pump f osc 2 ------------- - = r swx mosfet switch resistance = () ------------------------------- - 4xesr c1 esr c2 +++ ? (eq. 3) r 0 2x23 1 510 3 10 10 6 ? -------------------------------------------------- - 4xesr c1 esr c2 +++ ? (eq. 4) r 0 46 20 5 ++ esr c ? c 2 ----------------------------------------- 2esr c2 i out + ?? ?? ? (eq. 5) r out r out of icl7660s () n number of devices () --------------------------------------------------------- = (eq. 6) v out nv in () ? = (eq. 7) icl7660s, icl7660a
10 fn3179.7 january 23, 2013 this is of major importance for surface mount applications where capacitor size and cost are critical. smaller capacitors, such as 0.1f, can be used in conjunction with the boost pin to achieve similar output currents compared to the device free running with c 1 = c 2 = 10f or 100f. (see figure 11). increasing the oscillator frequency can also be achieved by overdriving the oscillator from an external clock, as shown in figure 16. in order to prevent device latchup, a 1k resistor must be used in series with t he clock output. in a situation where the designer has generated the external clock frequency using ttl logic, the addition of a 10k pull-up resistor to v+ supply is required. note that the pump frequency with external clocking, as with internal clocking, will be one-half of the clock frequency. output transitions occur on the positive going edge of the clock. it is also possible to increase the conversion efficiency of the icl7660s and icl7660a at low load levels by lowering the oscillator frequency. this reduces the switching losses, and is shown in figure 17. however, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (c 1 ) and reservoir (c 2 ) capacitors; this is overcome by increasing the values of c 1 and c 2 by the same factor by which the frequency has been reduced. for example, the addition of a 100pf capacitor between pin 7 (osc and v+) will lower the oscillator frequency to 1khz from its nominal frequency of 10khz (a multiple of 10), and thereby necessitate a corresponding increase in the value of c 1 and c 2 (from 10f to 100f). positive voltage doubling the icl7660s and icl7660a may be employed to achieve positive voltage doubling using the circuit shown in figure 18. in this application, the pu mp inverter switches of the icl7660s and icl7660a are used to charge c 1 to a voltage level of v+ -v f , where v+ is the supply voltage and v f is the forward voltage on c 1 , plus the supply voltage (v+) is applied through diode d 2 to capacitor c 2 . the voltage thus created on c 2 becomes (2v+) - (2v f ) or twice the supply voltage minus the combined forward voltage drops of diodes d 1 and d 2 . the source impedance of the output (v out ) will depend on the output current, but for v+ = 5v and an output current of 10ma, it will be approximately 60 . combined negative voltage conversion and positive supply doubling figure 19 combines the functions shown in figure 15 and figure 18 to provide negative voltage conversion and positive voltage doubling simultaneously. this approach would be suitable, for example, for generating +9v and -5v from an existing +5v supply. in this instance, capacitors c 1 and c 3 perform the pump and reservoir functions, respectively, for negative voltage generation, while capacitors c 2 and c 4 are pump and reservoir, respectively, for the doubled positive voltage. there is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher, due to the finite impedance of the common charge pump driver at pin 2 of the device. 1 2 3 4 8 7 6 5 + - 10f icl7660s v out v+ + - 10f v+ cmos gate 1k ? figure 16. external clocking icl7660a 1 2 3 4 8 7 6 5 + - icl7660s v out v+ + - c 2 c 1 c osc figure 17. lowering oscillator frequency icl7660a 1 2 3 4 8 7 6 5 icl7660s v+ d 1 d 2 c 1 c 2 v out = (2v+) - (2v f ) + - + - figure 18. positive voltage doubler note: d 1 and d 2 can be any suitable diode. icl7660a icl7660s, icl7660a
11 fn3179.7 january 23, 2013 voltage splitting the bidirectional characteristics can also be used to split a high supply in half, as shown in figure 20. the combined load will be evenly shared between the two sides, and a high value resistor to the lv pin ensures start-up. because the switches share the load in pa rallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. by using this circuit, and then the circuit of figure 15, +15v can be converted, via +7.5 and -7.5, to a nominal -15v, although with rather high series output resistance ( 250 ). regulated negative voltage supply in some cases, the output impedance of the icl7660s and icl7660a can be a problem, particularly if the load current varies substantially. the circuit of figure 21 can be used to overcome this by controlling the input voltage, via an icl7611 low-power cmos op amp, in such a way as to maintain a nearly constant output voltage. direct feedback is inadvisable, since the icl7660s?s and icl7660a?s output does not respond instantaneously to change in input, but only after the switching delay. the circuit shown supplies enough delay to accommodate the icl7660s and icl7660a, while maintaining adequate feedback. an increase in pump and storage capacitors is desirable, and the values shown provide an output impedance of less than 5 to a load of 10ma. other applications further information on the operation and use of the icl7660s and icl7660a may be found in application note an051, ?principles and applic ations of the icl7660 cmos voltage converter? . 1 2 3 4 8 7 6 5 icl7660s v+ d 1 d 2 c 4 v out = (2v+) - (v fd1 ) - (v fd2 ) + - c 2 + - c 3 + - v out = -v in c 1 + - figure 19. combined negative voltage converter and positive doubler d 3 icl7660a 1 2 3 4 8 7 6 5 + - + - 50f 50f + - 50f r l1 v out = v+ - v- 2 icl7660s v+ v- r l2 figure 20. splitting a supply in half icl7660a 1 2 3 4 8 7 6 5 + - 100f icl7660s 100f v out + - 10f icl7611 + - 100 50k +8v 100k 50k icl8069 56k +8v 800k 250k voltage adjust + - figure 21. regulating the output voltage icl7660a icl7660s, icl7660a
12 fn3179.7 january 23, 2013 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html icl7660s, icl7660a dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
13 fn3179.7 january 23, 2013 icl7660s, icl7660a package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. co nverted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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